ESI joins Georgia Institute of Technology 3D Systems Packaging Research Center

Laser drilling system maker ESI has joined the Georgia Institute of Technology 3D Systems Packaging Research Center as a full member.

Electro Scientific Industries (ESI; Portland, OR) has joined the Georgia Institute of Technology 3D Systems Packaging Research Center (PRC; Atlanta, GA) as a full member. As part of the partnership, ESI has installed a CornerStone ICP UV laser drilling system at the center to further enable on-campus R&D into via formation for future redistribution layers (RDLs) used in microelectronics.

The CornerStone ICP system is a good fit for the center's research into the most demanding next-generation applications. "Working with the ESI team, 8- to 10µm-diameter vias at 20µm pitch for multilayer RDL have already been demonstrated on glass interposers," comments Dr. Venky Sundaram, PRC associate director for industry programs. Prof. Rao Tummala, center director of PRC, adds, "This technology is a key part of the consumer-driven, high-performance, and automotive applications that we are pursuing." And Michael Darwin, general manager of the Industrial Products Division at ESI, states that "As the semiconductor and associated packaging technology moves to next-generation substrates in support of new products and industries, the requirements for size, shape, accuracy, and precision have become increasingly demanding."

PRC is a center for applied research into IC packaging technologies and best practices. With its industry partners, it is pioneering research into glass packaging as the next platform beyond organic packaging, and demonstrated the first prototypes of high-density glass substrates in 2013. This technology is being commercialized by several partners in Taiwan and Japan, while the center is focusing on continued research into the next-generation of 2.5D and 3D interposers, targeted to use ultra-fine interconnect pitches down to 20µm.

Laser systems are widely employed for drilling vias in organic substrates used for IC packages, with via dimensions in leading-edge substrates around 40-50µm in diameter. The Georgia Tech PRC-ESI co-development program will include research into combining the superior dimensional stability of glass substrates with the small via and high-accuracy capabilities of the CornerStone ICP system, demonstrating on large panels the very fine pitch sizes that are currently only possible using silicon interposers.

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